An Efficient Way to Increase Performance by Using Low Power Reconfigurable Routers

An Efficient Way to Increase Performance by Using Low Power Reconfigurable Routers

In this paper, the advantage of the use of an NoC with reconfigurable Routers has been presented instead of homogeneous ones. . In this paper we propose the use of a reconfigurable router, where the buffer slots are dynamically allocated to increase router efficiency in an NoC, even under rather different communication loads. In the proposed architecture, the depth of each buffer word used in t...

Highly Efficient Reconfigurable Routers in NoCs

NoC designs are based on a compromise of latency, power dissipation or energy, usually defined at design time. However, setting all parameters at design time can cause either excessive power dissipation (originated by router underutilization), or a higher latency. The situation worsens whenever the application changes its communication pattern, i.e., a portable phone downloads a new service. Th...

Membrane reactors: A way to increase efficiency

An Adaptive Physical Channel Regulator for High Performance and Low Power Network-On-Chip Routers

Chip Multi-Processor (CMP) architectures have become mainstream for designing processors. With a large number of cores, Network-On-Chip (NOC) provides a scalable communication method for CMP architectures, where wires become abundant resources available inside the chip. NOC must be carefully designed to meet constraints of power and area, and provide ultra low latencies. In this paper, we propo...

Low Power Reconfigurable Analog-to-Digital Converter

The objective of this project is to create a low power A/D converter␣ to be employed in a battery power ed wireless sensor. The key requirement of the converter is that it be able to cater to a wide␣ range of input data-rate (1sample/ s to >1Msample/s), and produce a␣ r esolution ranging from 8 bits to as high as 16bits, consuming the lowest possible power consumption. A possible subset of appl...